Name
Abstract | ||
|---|---|---|
Low-power on-chip cache is a crucial part in many applications. Conventional write operation depends on discharging/charging large bit lines capacitance which causes high power consumption. We propose a 7T SRAM cell that only depends on one of the bit lines during a write operation and reduce the write power consumption. HSPICE simulation shows that at least 49% write power saving, higher stability, and no performance degradation with additional 12.25% silicon area |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/SOCC.2005.1554488 | Herndon, VA |
Keywords | Field | DocType |
SRAM chips,cache storage,integrated circuit design,low-power electronics,7T SRAM cell,HSPICE simulation,low power cache design,on-chip cache,write operation | Tag RAM,Capacitance,Cache,Computer science,CPU cache,Electronic engineering,Integrated circuit design,Sram cell,Power consumption,Low-power electronics | Conference |
ISSN | ISBN | Citations |
2164-1676 | 0-7803-9264-7 | 13 |
PageRank | References | Authors |
2.09 | 3 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ramy E. Aly | 1 | 44 | 5.16 |
| Md. Ibrahim Faisal | 2 | 15 | 3.26 |
| Magdy A. Bayoumi | 3 | 803 | 122.04 |