Paper Info
Title
A cache-defect-aware code placement algorithm for improving the performance of processors
Abstract
Yield improvement through exploiting fault-free sections of defective chips is a well-known technique (Koren and Singh (1990) and Stapper et al. (1980)). The idea is to partition the circuitry of a chip in a way that fault-free sections can function independently. Many fault tolerant techniques for improving the yield of processors with a cache memory have been proposed. In this paper, we propose a defect-aware code placement technique which offsets the performance degradation of a processor with a defective cache memory. To the best of our knowledge, this is the first compiler-based technique which offsets the performance degradation due to cache defects. Experiments demonstrate that the technique can compensate the performance degradation even when 5% of cache lines are faulty. In some cases the technique was able to offset the impact even in presence of 25% faulty cache-lines.
Year
DOI
Venue
2005
10.1109/ICCAD.2005.1560207
ICCAD
Keywords
Field
DocType
cache storage,fault tolerant computing,microprocessor chips,cache defect,cache memory,cache-defect-aware code placement algorithm,compiler-based technique,fault tolerant computing,fault-free section,faulty cache-line,microprocessor chips,processor performance degradation
Cache-oblivious algorithm,Cache pollution,Snoopy cache,Computer science,Cache,Parallel computing,Page cache,Cache algorithms,Real-time computing,Cache coloring,Smart Cache
Conference
ISSN
ISBN
Citations 
1063-6757
0-7803-9254-X
10
PageRank 
References 
Authors
0.70
16
2
Name
Order
Citations
PageRank
Tohru Ishihara171987.96
Farzan Fallah255743.73