Title
A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints
Abstract
A methodology for power efficient partitioning of real-time data-dominated system specifications is presented. The proposed methodology aims at reducing the memory requirements in realizations of such applications by applying extensive code transformations in the initial system specification before partitioning over processors. This reorganization basically aligns the data production and consumption between the different procedures of the initial specification thus reducing the memory size requirements (and the resulting power) of the system's realizations especially those in the interfaces between different processors. The main novel contribution is that performance issues are explicitly taken into account during power oriented system-level transformations. The proposed methodology can be applied both in a parallel (programmable) processor context and also in heterogeneous hardware-software architectures.
Year
DOI
Venue
1999
10.1145/313817.313946
San Diego, CA, USA
Keywords
Field
DocType
embedded systems,hardware-software codesign,logic partitioning,low-power electronics,performance evaluation,code transformations,data production,data-dominated algorithm specifications,heterogeneous hardware-software architectures,initial system specification,memory requirements,memory size requirements,performance constraints,power efficient partitioning,power oriented system-level transformations,programmable processor context,software architecture,low cost,real time data,low power electronics,power efficiency
Power efficient,Computer science,Electronic engineering,System requirements specification,Low-power electronics,Distributed computing
Conference
ISBN
Citations 
PageRank 
1-58113-133-X
4
0.60
References 
Authors
3
5
Name
Order
Citations
PageRank
konstantinos masselos140.60
koen danckaert240.60
francky catthoor340.60
C. E. Goutis49714.78
H. Deman561.35