Name
Abstract | ||
|---|---|---|
This paper presents a physically based model of the MOSFET output conductance. The drain current and the output conductance of the MOS transistor are accurately described by single-piece functions of the inversion charge densities at source and drain. Carrier velocity saturation, channel length modulation (CLM) and drain induced barrier lowering (DIBL) are included in a single-piece analytical model. The results can be readily applied for first order analog circuit hand calculation |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ICECS.1998.813381 | Electronics, Circuits and Systems, 1998 IEEE International Conference |
Keywords | DocType | Volume |
mosfet,carrier mobility,electric admittance,inversion layers,semiconductor device models,mos transistors,mosfet output conductance,carrier velocity saturation,channel length modulation,drain current,drain induced barrier lowering,first order analog circuit hand calculation,inversion charge densities,output conductance,physically based model,single-piece charge-based model,impact ionization,analog circuits,first order,interpolation,charge density,voltage | Conference | 1 |
ISBN | Citations | PageRank |
0-7803-5008-1 | 3 | 0.97 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Schneider, M.C. | 1 | 3 | 0.97 |
| Galup-Montero, C. | 2 | 3 | 0.97 |
| Filho, O.C.G. | 3 | 3 | 1.31 |
| A. I. A. Cunha | 4 | 102 | 23.57 |