Name
Abstract | ||
|---|---|---|
In this paper a new efficient approach to bit-parallel fault simulation for sequential circuits is introduced and evaluated with the help of ISCAS89 benchmarks. Digital systems are modelled using Hierarchical Ternary Decision Diagrams (HTDDs). It leads to substantial reduction of both the number of simulated faults and calculations needed for simulation. Moreover, an approach presented in this paper is able to handle High-Level Primitives (HLPs) in addition to simple gates (GLPs), so it can be applied for hierarchical and multi-level simulation |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ICECS.1998.814866 | Electronics, Circuits and Systems, 1998 IEEE International Conference |
Keywords | DocType | Volume |
automatic testing,binary decision diagrams,fault simulation,logic testing,sequential circuits,htdd,hierarchical ternary decision diagrams,iscas89 benchmarks,bit-parallel fault simulation,hierarchical simulation,high-level primitives,multilevel simulation,parallel fault simulator,simulated faults,computational modeling,decision diagram,system testing,binary decision diagram,boolean functions,data structures | Conference | 2 |
ISBN | Citations | PageRank |
0-7803-5008-1 | 1 | 0.36 |
References | Authors | |
11 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sapiecha, J. | 1 | 1 | 0.36 |
| Sapiecha, K. | 2 | 1 | 0.36 |
| Deniziak, S. | 3 | 1 | 0.70 |