Name
Abstract | ||
|---|---|---|
Asynchronous Finite State Machines (AFSMs) have been proposed to be used in designs where the demands on high speed or low power consumption are high. In this paper we present a synthesis procedure for a type of AFSMs called locally clocked state machines with dynamic latch implementation. The use of dynamic latches makes it possible to reduce input capacitances and the number of transistors. It also enables efficient implementation of gates with monotonic output transitions which is important in AFSM design. We (1) show what implications the use of dynamic gates have on the synthesis procedure, (2) define state constraints and requirements on these circuits, and (3) present a complete procedure for implementing AFSMs through an example |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ICECS.1999.814489 | Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference |
Keywords | DocType | Volume |
asynchronous circuits,finite state machines,flip-flops,integrated logic circuits,logic design,asynchronous finite state machines,dynamic gates,dynamic latch implementation,high speed,input capacitance reduction,locally clocked fsm,locally clocked state machines,low power consumption,monotonic output transitions,state constraints,synthesis procedure,capacitance,finite state machine,automata,state machine,information technology,design methodology | Conference | 3 |
ISBN | Citations | PageRank |
0-7803-5682-9 | 3 | 0.43 |
References | Authors | |
3 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pasanen, J. | 1 | 3 | 0.43 |
| Oelmann, B. | 2 | 5 | 1.03 |