Name
Abstract | ||
|---|---|---|
Summary form only for tutorial. After an introduction of the issues involved in the first section, the second section covers design-for-manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield. However, once the changes are made it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools. Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact. The third section covers design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect aware test generation to both meet product quality and expose yield issues at test. Section four covers the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects. The applications of the basic concepts and techniques for silicon debug are covered in section five. Section six covers the application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact. Finally, in section seven, future trends, challenges and directions are covered. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/VLSID.2006.73 | Hyderabad, India |
Keywords | Field | DocType |
automatic test pattern generation,boundary scan testing,design for manufacture,design for testability,elemental semiconductors,failure analysis,fault diagnosis,integrated circuit reliability,integrated circuit testing,integrated circuit yield,silicon,algorithmic integrated circuit diagnosis,automatic test pattern generation,critical path based techniques,defect aware test generation,delay defects,design for testability,design-for-manufacturing techniques,scan chain diagnosis,semiconductor yield losses,silicon failure,statistical diagnosis techniques,yield improvement | Testability,Design for testing,Automatic test pattern generation,Computer science,Scan chain,Electronic engineering,Silicon debug,Critical path method,Design for manufacturability,Reliability engineering,Debugging | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-7695-2502-4 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Abercrombie | 1 | 0 | 0.34 |
| Bernd Koenemann | 2 | 0 | 0.34 |
| Nagesh Tamarapalli | 3 | 772 | 58.83 |
| Srikanth Venkataraman | 4 | 572 | 48.05 |