Name
Abstract | ||
|---|---|---|
We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to reduce the multi-clock path detection problems to SAT problems. We also show heuristics on the conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS89 benchmarks and other sample circuits. Experimental results show the improvement on the manipulatable size of circuits by using SAT. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ASPDAC.2000.835075 | Yokohama, Japan |
Keywords | DocType | ISBN |
clocks,computability,delay estimation,logic cad,multivalued logic circuits,sequential circuits,cnf formulae,iscas89 benchmarks,heuristics,multi-clock path analysis,multi-clock path detection problem,propositional satisfiability,sequential logic circuit | Conference | 0-7803-5973-9 |
Citations | PageRank | References |
2 | 0.39 | 10 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kazuhiro Nakamura | 1 | 13 | 1.88 |
| Shinji Maruoka | 2 | 2 | 1.06 |
| Shinji Kimura | 3 | 60 | 17.59 |
| Katsumasa Watanabe | 4 | 15 | 4.73 |