Name
Abstract | ||
|---|---|---|
A new bi-directional bit serial-parallel multiplication architecture is presented. The proposed structure is regular and modular, and requires nearest neighbour communication links only, which makes it more efficient for VLSI implementation. Furthermore, a judicious deployment of latches in the circuit ensures that the multiplier operates on two coefficients of the multiplicand at the same time thus speeding up the process. Comparison of the new multiplier structure with previous ones has shown the superiority of the new architecture |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ISCAS.2000.857504 | ISCAS |
Keywords | Field | DocType |
vlsi,cellular arrays,delays,multiplying circuits,bi-directional serial-parallel multiplier,multiplicand,multiplier structure,nearest neighbour communication links,computer science,throughput,very large scale integration,computer architecture,low latency | Nearest neighbour,Architecture,Computer science,Parallel computing,Multiplier (economics),Electronic engineering,Multiplication,Latency (engineering),Modular design,Throughput,Very-large-scale integration | Conference |
Volume | ISBN | Citations |
5 | 0-7803-5482-6 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ahmed Bouridane | 1 | 837 | 99.53 |
| Mokhtar Nibouche | 2 | 50 | 11.87 |
| Omar Nibouche | 3 | 89 | 13.50 |
| Danny Crookes | 4 | 279 | 39.13 |
| Badr Albesher | 5 | 3 | 0.72 |