Name
Abstract | ||
|---|---|---|
In this paper, two optimum implementation schemes are proposed in soft output Viterbi algorithm (SOVA) with high performance. One is modifying the architecture known as two-step SOVA scheme in order to obtain high speed. The other is lowering the reliability values to a same level with a scaling factor 0.25 or 0.33 for hardware implementation in order to compensate for the distortion. Also, we have implemented one step SOVA and the modified architecture for comparison of two schemes with 0.65 μm Samsung SOG technology using Verilog HDL. At result, The modified architecture provides higher SNR performance by 2 dB at the BER 1E-04 than that of the general SOVA. Also we have obtained good performance by using a fixed scaling factor, by which the soft output of SOVA can be considered as being multiplied. The simulation results show that the modified architecture with both methods contributes to high performance |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ISCAS.2000.858682 | ISCAS |
Keywords | Field | DocType |
viterbi decoding,convolutional codes,hardware description languages,low-power electronics,parallel architectures,turbo codes,snr performance,samsung sog technology,verilog hdl,fixed scaling factor,hardware implementation,modified two-step sova-based turbo decoder,reliability values,soft output viterbi algorithm,communication networks,viterbi algorithm,bit error rate,concatenated codes,decoding,low power electronics | Scale factor,Concatenated error correction code,Convolutional code,Computer science,Soft output Viterbi algorithm,Turbo code,Electronic engineering,Viterbi decoder,Verilog,Viterbi algorithm | Conference |
Volume | ISBN | Citations |
4 | 0-7803-5482-6 | 11 |
PageRank | References | Authors |
0.84 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| daewon | 1 | 15 | 2.25 |
| Taek Won Kwon | 2 | 53 | 4.76 |
| Jim Rim Choi | 3 | 11 | 0.84 |
| Jun Jin Kong | 4 | 51 | 5.83 |