Paper Info
Title
Hierarchical conditional dependency graphs as a unifying design representation in the CODESIS high-level synthesis system
Abstract
In high-level hardware synthesis (HLS), there is a gap in the quality of the synthesized results between data-flow and control-flow dominated behavioral descriptions. Heuristics destined for the former usually perform poorly on the latter. To close this gap, the CODESIS interactive HLS tool relies on a unifying intermediate design representation and adapted heuristics that are able to accommodate both types of designs, as well as designs of a mixed data-flow and control-flow nature. Preliminary experimental results in mutual exclusiveness detection and in efficiently scheduling conditional behaviors, are encouraging and prompt for more extensive experimentation
Year
DOI
Venue
2000
10.1109/ISSS.2000.874030
Madrid
Keywords
Field
DocType
flow graphs,high level synthesis,interactive systems,scheduling,CODESIS interactive high-level synthesis system,adapted heuristics,conditional behaviour scheduling,control-flow dominated behavioural descriptions,data-flow dominated behavioural descriptions,hierarchical conditional dependency graphs,high-level hardware synthesis,mutual exclusiveness detection,synthesised results quality,unifying intermediate design representation
Graph,Computer science,Scheduling (computing),High-level synthesis,Theoretical computer science,Real-time computing,Heuristics,Hardware synthesis,Distributed computing
Conference
ISSN
ISBN
Citations 
1080-1820
0-7695-0765-4
9
PageRank 
References 
Authors
0.85
21
2
Name
Order
Citations
PageRank
Apostolos A. Kountouris110710.82
Christophe Wolinski229728.34