Name
Abstract | ||
|---|---|---|
This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TC.2006.126 | Computers, IEEE Transactions |
Keywords | Field | DocType |
digital arithmetic,multiplying circuits,array integer multiplier design,computer arithmetic,overflow detection circuit,overflow detection technique,tree integer multiplier design,Computer arithmetic,combinational logic,high-speed arithmetic algorithms,multiplication.,overflow detection | Integer overflow,Arbitrary-precision arithmetic,Computer science,Operand,Arithmetic,Combinational logic,Multiplier (economics),Binary scaling,Multiplication,Saturation arithmetic | Journal |
Volume | Issue | ISSN |
55 | 8 | 0018-9340 |
Citations | PageRank | References |
5 | 0.56 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mustafa Gök | 1 | 8 | 0.99 |
| Michael J. Schulte | 2 | 1015 | 87.86 |
| Mark G. Arnold | 3 | 238 | 30.87 |