Name
Abstract | ||
|---|---|---|
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-on-Chips (MPSoCs), we focus on the problem of implementing efficient interconnect systems for devices which are ever more densely packed with parallel computing cores. Easily seen that traditional buses can not provide enough bandwidth, a revolutionary path to scalability is provided by packet-switched Network-on-Chips (NoCs), while a more conservative approach dictates the addition of bandwidth-rich components (e.g. crossbars) within the pre-existing fabrics. While both alternatives have already been explored, a thorough contrastive analysis is still missing. In this paper, we bring crossbar and NoC designs to the chip layout level in order to highlight the respective strengths and weaknesses in terms of performance, area and power, keeping an eye on future scalability. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/DATE.2006.244033 | Design, Automation and Test in Europe, 2006. DATE '06. Proceedings |
Keywords | Field | DocType |
integrated circuit interconnections,integrated circuit layout,microprocessor chips,network-on-chip,MPSoC,NoC designs,chip layout level,interconnect fabric,layout awareness,multiprocessor system-on-chips,packet-switched network-on-chips,parallel computing cores,revolutionary path | Integrated circuit layout,Computer architecture,Computer science,Parallel computing,Network on a chip,Network topology,Chip,Bandwidth (signal processing),MPSoC,Crossbar switch,Embedded system,Scalability | Conference |
Volume | ISSN | ISBN |
1 | 1530-1591 | 3-9810801-1-4 |
Citations | PageRank | References |
50 | 2.06 | 14 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. Angiolini | 1 | 144 | 8.26 |
| Meloni, P. | 2 | 57 | 3.16 |
| Salvatore Carta | 3 | 579 | 47.28 |
| Luca Benini | 4 | 13116 | 1188.49 |