Name
Title | ||
|---|---|---|
An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors |
Abstract | ||
|---|---|---|
Processors with multiple functional units, such as CRAY-1, Cyber 205, and FPS 164, have been used for high-end scientific computation tasks. Much effort has been put into increasing the throughput of such systems. One critical consideration in their design is the identification and implementation of a suitable instruction issuing scheme. Existing approaches do not issue enough instructions per machine cycle to fully utilize the functional units and realize the high-performance level achievable with these powerful execution resources. |
Year | DOI | Venue |
|---|---|---|
1986 | 10.1109/TC.1986.1676841 | Instruction-level parallel processors |
Keywords | Field | DocType |
dispatch stack,dynamic instruction scheduling,instruction issuing,instruction unit,multiple functional unit processors,multiple instruction dispatching,processor performance enhancement,functional unit,process simulation,scientific computing,statistical computing,data processing | Instruction unit,Computer architecture,Data processing,Supercomputer,Computer science,Parallel computing,Throughput,Instruction cycle,Embedded system,Mathematical logic | Journal |
Volume | Issue | ISSN |
C | 9 | 0018-9340 |
ISBN | Citations | PageRank |
0-8186-6527-0 | 33 | 5.89 |
References | Authors | |
16 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Acosta, R.D. | 1 | 33 | 5.89 |
| Kjelstrup, J. | 2 | 33 | 5.89 |
| Torng, H.C. | 3 | 47 | 14.42 |