Name
Abstract | ||
|---|---|---|
This paper presents the novel behavioral architecture of LSCIC (Layered Scalable Concurrent Image Compression) pre processor chip by utilizing scalable compression algorithm. This design separates enhanced and base layer pixels prior to concurrent compression operation in the coders. This paper also proposes a mathematical technique to snub the data signal errors by virtue of vector norm and Eigen values by controlling matrix condition number. Before attempting the behavioral design, a mathematical model is developed with timing and control signal constraints to avoid collision of signals. Simulation and synthesis procedures with successful synthesis report are also presented to verify the effectiveness of algorithm showing the correct operation of designed architecture. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ICICIC.2006.306 | Innovative Computing, Information and Control, 2006. ICICIC '06. First International Conference |
Keywords | Field | DocType |
data compression,digital signal processing chips,eigenvalues and eigenfunctions,hardware description languages,image coding,logic design,matrix algebra,program processors,vectors,LSCIC pre-processor design,constriction elucidation,control signal constraint,data signal error snubbing,eigen values,layered scalable concurrent image compression pre processor chip,mathematical model,matrix condition number,scalable compression algorithm,signal collision,timing constraint,vector norm | Logic synthesis,Condition number,Computer science,Chip,Artificial intelligence,Norm (mathematics),Data compression,Machine learning,Image compression,Hardware description language,Scalability | Conference |
Volume | ISBN | Citations |
2 | 0-7695-2616-0 | 4 |
PageRank | References | Authors |
0.55 | 1 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Muhammad Kamran | 1 | 31 | 7.00 |
| Feng Shi | 2 | 4 | 0.55 |