Name
Abstract | ||
|---|---|---|
This paper presents a local buffer memory in the form of a stream register file (SRF) that was developed in order to connect, in a compiler-friendly pattern, large-bandwidth run-time configurable logic units in processor-based SOCs. The proposed SRF offers to the host SOC system performance speedups in the range of 4times, with area/power overhead in the order of 6%. The described hardware and algorithm mapping strategy was implemented on silicon in a SOC based on the PiCoGA reconfigurable architecture. The SOC provides an average 450 MOPS (mega operations per Second) in STM CMOS090 technology running at 100MHZ |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1693425 | Island of Kos |
Keywords | Field | DocType |
buffer storage,microprocessor chips,reconfigurable architectures,system-on-chip,PiCoGA reconfigurable architecture,SOC,algorithm mapping,buffer memory,hardware mapping,reconfigurable processors,run-time configurable logic units,stream register file | Logic synthesis,System on a chip,Computer science,Parallel computing,Parallel processing,Register file,Electronic engineering,Computer hardware | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-9389-9 | 1 |
PageRank | References | Authors |
0.36 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fabio Campi | 1 | 227 | 19.26 |
| Zoffoli, P. | 2 | 1 | 0.36 |
| Claudio Mucci | 3 | 91 | 8.32 |
| Bocchi, M. | 4 | 1 | 0.36 |