Name
Abstract | ||
|---|---|---|
A 16Mb MRAM based on 0.13mum CMOS and 0.24mum MRAM process achieves a 34ns asynchronous access and 100MHz synchronous operation, compatible with pseudo-SRAM for mobile applications. By implementation of FORK wiring scheme, the cell efficiency is raised to 39.9% and the disturb robustness of half-selection state is improved |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISSCC.2006.1696080 | San Francisco, CA |
Keywords | DocType | ISSN |
cmos integrated circuits,magnetic storage,magnetoresistive devices,mobile communication,random-access storage,wiring,0.13 micron,0.24 micron,100 mhz,16 mbit,34 ns,cmos,fork wiring scheme,mram,asynchronous access,burst modes,half selection state,mobile applications,pseudo-sram,synchronous operation | Conference | 0193-6530 |
ISBN | Citations | PageRank |
1-4244-0079-1 | 3 | 3.32 |
References | Authors | |
0 | 15 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| yuko t iwata | 1 | 3 | 3.32 |
| kenji tsuchida | 2 | 4 | 4.03 |
| tsutomu inaba | 3 | 3 | 3.32 |
| yoshiyuki shimizu | 4 | 3 | 3.32 |
| r takizawa | 5 | 3 | 3.32 |
| yasukiyo ueda | 6 | 3 | 3.32 |
| Tadahiko Sugibayashi | 7 | 127 | 28.40 |
| Yoshiaki Asao | 8 | 7 | 4.44 |
| takeshi kajiyama | 9 | 3 | 3.32 |
| Keiji Hosotani | 10 | 6 | 4.07 |
| shiro ikegawa | 11 | 3 | 3.32 |
| tadashi kai | 12 | 3 | 3.32 |
| Marvin K. Nakayama | 13 | 277 | 53.20 |
| Shuichi Tahara | 14 | 4 | 4.36 |
| Hiroaki Yoda | 15 | 8 | 5.40 |