A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL - Citegraph

Paper Info

Title
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL

Abstract
A series pipelined CAS latency control with voltage-controlled delay line that extends maximum data rate to 2.5Gb/s/pin at 1.7V, is presented. Other schemes applied in the DLL are dual loop control that increases power noise immunity and LPDCC that achieves low power consumption. All these schemes are implemented in a 8M times 32 device using a 0.10 mum DRAM process

Year	DOI	Venue
2006	10.1109/ISSCC.2006.1696091	San Francisco, CA
Keywords	DocType	ISSN
dram chips,delay lines,delay lock loops,low-power electronics,voltage control,0.10 micron,1.7 v,2.4 gbit/s,cas latency control,gddr3 sdram,lpdcc,dual loop digital dll,power noise immunity,series pipeline,voltage controlled delay line,low power electronics	Conference	0193-6530
ISBN	Citations	PageRank
1-4244-0079-1	10	1.91
References	Authors
1	12

Authors (12 rows)

Cited by (10 rows)

References (1 rows)

Name	Order	Citations	PageRank
Dong Uk Lee	1	80	7.98
Hyun-Woo Lee	2	162	43.02
ki chang kwean	3	10	1.91
young kyoung choi	4	10	1.91
hyong uk moon	5	10	1.91
seung wook kwack	6	10	1.91
Shin-Deok Kang	7	25	3.90
kwan weon kim	8	10	1.91
yong ju kim	9	10	1.91
Patrick B. Moran	10	15	2.74
Jin Hong Ahn	11	27	4.80
Joong Sik Kih	12	10	2.25

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