Name
Abstract | ||
|---|---|---|
A dual-loop analog-digital hybrid PLL with a small-bandwidth digital loop and large-bandwidth analog loop achieves low jitter by suppressing 1/f noise and does not require off-chip loop filter components. The operating range using a narrow-range VCO is from 10 to 200MHz. The output jitter over this range is <0.028UIpp. The chip is implemented in a 0.18mum CMOS process and consumes 50mW from a 1.8V supply |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISSCC.2006.1696304 | San Francisco, CA |
Keywords | DocType | ISSN |
1/f noise,cmos integrated circuits,integrated circuit noise,jitter,phase locked loops,voltage-controlled oscillators,0.18 micron,1.8 v,10 to 200 mhz,50 mw,cmos process,pvt-tolerant low-1/f noise,dual-loop hybrid pll,large-bandwidth analog loop,phase locked loop,small-bandwidth digital loop,voltage controlled oscillator,chip | Conference | 0193-6530 |
ISBN | Citations | PageRank |
1-4244-0079-1 | 1 | 0.50 |
References | Authors | |
1 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyung-Rok Lee | 1 | 8 | 2.12 |
| ook kim | 2 | 1 | 0.50 |
| keewook jung | 3 | 1 | 0.50 |
| jeonghee shin | 4 | 1 | 0.50 |
| Deog-Kyoon Jeong | 5 | 626 | 119.05 |