Name
Title | ||
|---|---|---|
Design of half-rate clock and data recovery circuits for optical communication systems |
Abstract | ||
|---|---|---|
This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the first implementation incorporates a ring oscillator and a linear phase detector whereas the second implementation uses a multiphase LC oscillator and a bang-bang phase/frequency detector. Fabricated in 0.18-&mgr;m CMOS technology, the power consumption of each of the circuits is less than 100˜mW. The rms jitter of the output clock for the two prototypes is 1˜ps and 0.8˜ps, respectively, while the latter achieves a capture range of more than 14%. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/DAC.2001.156120 | DAC |
Keywords | Field | DocType |
CMOS digital integrated circuits,digital communication,optical receivers,phase detectors,synchronisation,timing jitter,0.18 micron,10 Gbit/s,CMOS technology,bang-bang phase/frequency detector,capture range,half-rate clock and data recovery circuits,linear phase detector,multiphase LC oscillator,optical communication systems,optical receivers,output clock,power consumption,ring oscillator,rms jitter | Linear phase,Clock signal,Electronic oscillator,Ring oscillator,Half Rate,Computer science,Electronic engineering,CMOS,Real-time computing,Jitter,Detector | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-58113-297-2 | 4 |
PageRank | References | Authors |
0.60 | 1 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jafar Savoj | 1 | 154 | 27.84 |
| Behzad Razavi | 2 | 1003 | 285.69 |