Name
Abstract | ||
|---|---|---|
Traditional improvements in packet switch architecture are aimed at increasing switch performance in terms of utilization, fairness and QoS. This paper focuses on improving the architecture to achieve implementation feasibility of terabit aggregate data rates while maintaining such performance. Terabit class shared-memory switch chips are simple in concept but are a challenge to build due to the memory speed requirements and the complexity of wiring needed to connect these memories. Using a property of the combined shared memory and virtual output queuing switch architecture and a property of SRAMs, a new architecture is derived that enables construction of a terabit class switch fabric |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ICCCN.2001.956303 | Scottsdale, AZ |
Keywords | Field | DocType |
CMOS memory circuits,SRAM chips,circuit optimisation,electronic switching systems,integrated circuit design,network routing,packet switching,quality of service,queueing theory,shared memory systems,0.11 micron,QoS,SRAM,fairness,memory speed,optimized architecture,optimized design,output-queued CMOS switch chip,packet switch architecture,placement,routing,shared memory switch architecture,shared-memory switch chips,switch performance,switch utilization,terabit aggregate data rates,terabit class switch fabric,virtual output queuing switch architecture,wiring | Architecture,Shared memory,Computer science,Computer network,Quality of service,Chip,Queueing theory,Integrated circuit design,Packet switching,Terabit | Conference |
ISSN | ISBN | Citations |
1095-2055 | 0-7803-7128-3 | 1 |
PageRank | References | Authors |
0.46 | 9 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ronald P. Luijten | 1 | 24 | 4.06 |
| François Abel | 2 | 91 | 10.97 |
| Mitchell Gusat | 3 | 158 | 16.23 |
| Cyriel Minkenberg | 4 | 399 | 39.21 |