Name
Abstract | ||
|---|---|---|
sent a new transmission-line approach to gigahertz-rate clock generation. Using the inherently stable LC characteristics of on-chip VLSI interconnect, the clock distribution network be- comes a low-impedance distributed oscillator. The RTWO operates by creating a rotating traveling wave within a closed-loop differen- tial transmission line. Distributed CMOS inverters serve as both transmission-line amplifiers and latches to power the oscillation and ensure rotational lock. Load capacitance is absorbed into the transmission-line constants whereby energy is recirculated giving an adiabatic quality. Unusually for an LC oscillator, multiphase (360 ) square waves are produced directly. RTWO structures are compact and can be wired together to form rotary oscillator arrays (ROAs) to distribute a phase-locked clock over a large chip. The principle is scalable to very high clock frequencies. Issues related to interconnect and field coupling dominate the design process for RTWOs. Taking precautions to avoid unwanted signal couplings, the rise and fall times of 20 ps, suggested by simulation, may be realized at low power consumption. Experimental results of the 0.25- m CMOS test chip with 950-MHz and 3.4-GHz rings are presented, indicating 5.5-ps jitter and 34-dB power supply rejection ratio (PSRR). Design errors in the test chip precluded meaningful rise and fall time measurements. Index Terms—Clocks, MOSFET oscillators, phase-locked oscil- lators, phased arrays, synchronization, timing circuits, transmis- sion line resonators, traveling-wave amplifiers. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/4.962285 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
CMOS digital integrated circuits,VLSI,clocks,integrated circuit design,low-power electronics,phase locked oscillators,pulse generators,synchronisation,timing jitter,0.25 micron,20 ps,3.4 GHz,950 MHz,CMOS,LC characteristics,adiabatic quality,clock technology,closed-loop differential transmission line,distributed CMOS inverters,field coupling,gigahertz-rate clock generation,jitter,load capacitance,low-impedance distributed oscillator,multiphase square waves,on-chip VLSI interconnect,phase-locked clock,power consumption,power supply rejection ratio,rotary traveling-wave oscillator arrays,rotational lock,transmission-line amplifiers,transmission-line approach,transmission-line constants | Journal | 36 |
Issue | ISSN | Citations |
11 | 0018-9200 | 110 |
PageRank | References | Authors |
10.87 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wood, John | 1 | 110 | 10.87 |
| Terence C. Edwards | 2 | 110 | 10.87 |
| Steve Lipa | 3 | 110 | 10.87 |