Paper Info
Title
Placement driven retiming with a coupled edge timing model
Abstract
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear whether the predicted performance improvement will still be valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model taking into account the effect of retiming on capacitive loads of single wires as well as fanout systems. We propose the integration of retiming into a timing-driven standard cell placement environment based on simulated annealing. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on standard FEAS (Leiserson and Saxe, J. VLSI and Computer Sys., pp. 41-67, 1983; and Algorithmica vol. 6, no 1, pp. 5-35, 1991.), our approach achieved an improvement in cycle time of up to 34% and 17% on the average.
Year
DOI
Venue
2001
10.1109/ICCAD.2001.968604
San Jose, CA, USA
Keywords
Field
DocType
circuit layout,circuit optimisation,logic design,sequential circuits,simulated annealing,timing,FEAS algorithin,capacitive loads,circuit netlist modifications,coupled edge timing model,cycle time,fanout systems,optimization technique,performance improvement,performance optimization,placement driven retiming,placement process,retiming,retiming algorithm,retiming integration,sequential circuits,simulated annealing,timing model,timing-driven standard cell placement environment
Simulated annealing,Netlist,Retiming,Sequential logic,Computer science,Parallel computing,Real-time computing,Design flow,Electronic engineering,Standard cell,Very-large-scale integration,Performance improvement
Conference
ISSN
ISBN
Citations 
1092-3152
0-7803-7247-6
6
PageRank 
References 
Authors
0.50
16
2
Name
Order
Citations
PageRank
Ingmar Neumann1306.56
Wolfgang Kunz223633.71