Paper Info
Title
Trends and challenges in VLSI technology scaling towards 100 nm
Abstract
Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm generation and beyond. The first focus area is the process technology, including transistor scaling trends and research activities for the 100nm technology node and beyond. The transistor leakage and interconnect RC delays will continue to increase. The tutorial will review new circuit design techniques for emerging process technologies, including dual Vt transistors and silicon-on-insulator. It will also cover circuit and layout techniques to reduce clock distribution skew and jitter, model and reduce transistor leakage and improve the electrical performance of flip-chip packages. Finally, the tutorial will review the test challenges for the 100nm technology node due to increased clock frequency and power consumption (both active and passive) and present several potential solutions
Year
DOI
Venue
2002
10.1109/ASPDAC.2002.994875
Bangalore
Keywords
DocType
ISBN
VLSI,circuit CAD,clocks,flip-chip devices,integrated circuit design,integrated circuit interconnections,integrated circuit packaging,jitter,leakage currents,low-power electronics,100 nm,Moore's Law,VLSI technology scaling,circuit design techniques,circuit engineers,clock distribution skew,clock frequencies,electrical performance,flip-chip packages,interconnect RC delays,jitter,power consumption,process engineers,process technology,research activities,silicon-on-insulator,transistor densities,transistor leakage,transistor scaling trends
Conference
0-7695-1441-3
Citations 
PageRank 
References 
0
0.34
0
Authors
4
Name
Order
Citations
PageRank
Rusu, S.100.34
Sachdev, M.200.34
Svensson, C.300.34
Bram Nauta41770256.74