A 9.95–11.3-Gb/s XFP Transceiver in 0.13- CMOS - Citegraph

Paper Info

Title
A 9.95–11.3-Gb/s XFP Transceiver in 0.13- CMOS

Abstract
A 9.95-11.3-Gb/s transceiver in 0.13-mum CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL with a binary phase detector to exceed XFP jitter specifications. The dual loop solves the problem of having a controlled jitter transfer bandwidth with a binary phase detector. A half rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 12'' of FR4 is equalized resulting in system JGEN under 4 mUIRMS and 35 mUI PP. Power consumption is 800 mW

Year	DOI	Venue
2006	10.1109/JSSC.2006.884344	Solid-State Circuits, IEEE Journal of
Keywords	DocType	Volume
delay lock loops,frequency locked loops,phase locked loops,synchronisation,transceivers,0.13 micron,800 mW,XFP jitter,XFP transceiver,binary phase detector,clock and data recovery,delay-locked loop,dual-loop DLL/PLL,frequency-locked loop,phase-locked loop,Clock and data recovery (CDR),delay-locked loop (DLL),frequency-locked loop (FLL),phase-locked loop (PLL),transceiver	Journal	41
Issue	ISSN	Citations
12	0018-9200	0
PageRank	References	Authors
0.34	0	14

Authors (14 rows)

Cited by (0 rows)

References (0 rows)

Name	Order	Citations	PageRank
John G. Kenney	1	0	0.34
Declan Dalton	2	44	30.23
e anthony evans	3	0	0.34
Murat Hayri Eskiyerli	4	0	0.34
Barry Hilton	5	12	1.60
Dave Hitchcox	6	12	1.60
Terence Kwok	7	12	1.60
daniel m mulcahy	8	12	1.60
Chris Mcquilkin	9	0	0.34
Viswabharath Reddy	10	12	1.60
Siva Selvanayagam	11	12	1.60
Paul Shepherd	12	12	1.94
Ward S. Titus	13	14	2.75
Lawrence Devito	14	0	0.34

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