Name
Abstract | ||
|---|---|---|
For digital circuits with ultra-low power consumption, floating- gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP). |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VLSID.2007.143 | VLSI Design |
Keywords | Field | DocType |
MOS logic circuits,adders,logic design,low-power electronics,nanotechnology,120 nm,150 mV,250 mV,adder structure,digital circuits,energy-delay product,fan-in floating-gate circuits,power supply,static CMOS circuits,ultra-low power consumption | Adder,Computer science,Fan-in,Adiabatic circuit,Electronic engineering,CMOS,Subthreshold conduction,Transistor,Electrical engineering,Integrated injection logic,Low-power electronics | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-7695-2762-0 | 1 |
PageRank | References | Authors |
0.37 | 3 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alfredsson, J. | 1 | 1 | 0.37 |
| Snorre Aunet | 2 | 119 | 29.60 |
| B Oelmann | 3 | 77 | 21.78 |