Name
Abstract | ||
|---|---|---|
For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage common-source amplifiers are used in a sample-and-hold (S/H) circuit and a 1st multiplying digital-to-analog converter (MDAC). The common-source amplifier with two-stage transimpedance gain-boosting amplifiers realizes more than 90 dB. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under the condition, each ADC dissipates only 55 mW |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ESSCIR.2006.307509 | IEICE Transactions |
Keywords | Field | DocType |
cmos integrated circuits,analogue-digital conversion,digital-analogue conversion,operational amplifiers,radio receivers,sample and hold circuits,1.2 v,12 bit,55 mw,90 nm,cmos technology,i/q amplifier sharing technique,s/h circuit,common-source amplifier,low-power dissipation,multiplying digital-to-analog converter,pipeline adc,sample-and-hold circuit,single-stage common-source amplifiers,transimpedance gain-boosting amplifiers,wireless receivers,pipeline,amplifier | 12-bit,CMOS,Electronic engineering,Transimpedance amplifier,Sample and hold,Engineering,Electrical engineering,Operational amplifier,Differential amplifier,Amplifier,Low-power electronics | Journal |
Volume | Issue | ISSN |
91-C | 6 | 1930-8833 |
ISBN | Citations | PageRank |
1-4244-0303-0 | 6 | 0.77 |
References | Authors | |
4 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomohiko Ito | 1 | 16 | 4.40 |
| Daisuke Kurose | 2 | 17 | 5.11 |
| Takeshi Ueno | 3 | 9 | 1.84 |
| Takafumi Yamaji | 4 | 55 | 18.00 |
| Tetsuro Itakura | 5 | 187 | 33.44 |