Name
Abstract | ||
|---|---|---|
We study the problem of reducing power during data-retention in a standby static random access memory (SRAM). For successful data-retention, the supply voltage of an SRAM cell should be greater than a critical data retention voltage (DRV). Due to circuit parameter variations, the DRV for different cells on the same chip exhibits variation with a distribution having diminishing tail. For reliable data retention, the existing low-power design uses a worst-case technique in which a standby supply voltage that is larger than the highest DRV among all cells in an SRAM is used. Instead, our approach uses aggressive voltage reduction and counters the ensuing unreliability through a fault-tolerant memory architecture. The main results of this work are as follows: (i) We establish fundamental bounds on the power reduction in terms of the DRV-distribution using techniques from information theory. For the DRV-distribution of test-chip in (Qin, H, et al., 2006), we show that 49% power reduction with respect to (w.r.t.) the worst-case is a fundamental lower bound while 40% power reduction w.r.t. the worst-case is achievable with a practical combinatorial scheme, (ii) We study the power reduction as a function of the block-length for low-latency codes since most applications using SRAM are latency constrained. We propose a reliable memory architecture based on the Hamming code for the next test-chip implementation with a predicted power reduction of 33% while accounting for coding overheads. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ICASSP.2007.366178 | Acoustics, Speech and Signal Processing, 2007. ICASSP 2007. IEEE International Conference |
Keywords | Field | DocType |
Hamming codes,SRAM chips,data analysis,fault tolerance,Hamming code,aggressive voltage reduction,circuit parameter variations,coding overheads,data retention voltage,data-retention,fault-tolerant memory architecture,information theory,low-latency codes,power reduction,standby SRAM,static random access memory,supply voltage,test-chip,worst-case technique,Circuit Optimization,Error correction coding,Information Theory,Memory Architecture,SRAM Chips | Voltage reduction,Hamming code,Mathematical optimization,Data retention,Upper and lower bounds,Computer science,Parallel computing,Static random-access memory,Chip,Redundancy (engineering),Memory architecture,Reliability engineering | Conference |
Volume | ISSN | ISBN |
2 | 1520-6149 E-ISBN : 1-4244-0728-1 | 1-4244-0728-1 |
Citations | PageRank | References |
3 | 0.72 | 3 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Animesh Kumar | 1 | 133 | 23.95 |
| Qin, H. | 2 | 4 | 1.90 |
| Ishwar, P. | 3 | 4 | 1.90 |
| Jan M. Rabaey | 4 | 4796 | 1049.96 |