Name
Abstract | ||
|---|---|---|
A low-voltage design is developed for amplifiers in the pipelined ADC, regulating overdrive voltage to be constant over PVT variations. A prototype 10b 80MS/S pipelined ADC is fabricated in a 90nm CMOS process. The ADC consumes 6.5mW from a 0.8V supply and occupies 1.18 times 0.54mm2 |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISSCC.2007.373489 | San Francisco, CA |
Keywords | Field | DocType |
CMOS integrated circuits,amplifiers,analogue-digital conversion,low-power electronics,0.8 V,10 bit,6.5 mW,90 nm,CMOS process,PVT variations,amplifiers,low-voltage design,pipelined analog-to-digital converter,regulated overdrive voltage biasing | Computer science,Overdrive voltage,Electronic engineering,CMOS,Cmos process,Electrical engineering,Amplifier,Low-power electronics,Biasing | Conference |
ISSN | ISBN | Citations |
0193-6530 E-ISBN : 1-4244-0853-9 | 1-4244-0853-9 | 19 |
PageRank | References | Authors |
3.50 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masato Yoshioka | 1 | 91 | 12.46 |
| Masahiro Kudo | 2 | 41 | 7.70 |
| Toshihiko Mori | 3 | 48 | 7.62 |
| Sanroku Tsukamoto | 4 | 109 | 18.09 |