Name
Abstract | ||
|---|---|---|
The architecture and VLSI implementation of a programmable HD real-time motion estimator is presented. Due to the programmability, main video compression standards like MPEG-2, H.264, and VC-1 are supported. A sophisticated data flow concept in combination with a VLIW approach for controlling leads to a sustained utilization of the arithmetic resources of 95%. An area efficient architecture and design of the datapath consisting of 64 parallel processing elements reduced the required complexity to 1.2 million gates. With a first VLSI implementation in 90 nm standard cell semiconductor technology a maximum clock rate of 334 MHz was achieved. This design enables real-time motion estimation in HD format with 1920-1080 pixels at 25 Hz frame rate. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISCAS.2007.378826 | New Orleans, LA |
Keywords | Field | DocType |
VLSI,data compression,integrated circuit design,logic design,motion estimation,programmable circuits,real-time systems,video coding,25 Hz,334 MHz,90 nm,H.264,MPEG-2,VC-1,VLIW approach,VLSI implementation,data flow concept,parallel processing elements,programmable HD real-time motion estimator,standard cell semiconductor technology,video compression standards | Logic synthesis,Datapath,Quarter-pixel motion,Computer science,Electronic engineering,Standard cell,Frame rate,Motion estimation,Computer hardware,Very-large-scale integration,Clock rate,Embedded system | Conference |
ISSN | ISBN | Citations |
0271-4302 | 1-4244-0921-7 | 5 |
PageRank | References | Authors |
0.61 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gaedke, K. | 1 | 5 | 0.61 |
| Borsum, M. | 2 | 5 | 0.61 |
| Georgi, M. | 3 | 5 | 0.61 |
| Kluger, A. | 4 | 5 | 0.61 |