Paper Info
Title
86 dB DR Cross-Coupled Time-Interleaved xx ADC for Audio Signal Band with 322 ΣA Current Consumption
Abstract
An audio band sigma-delta ADC based on a new time-interleaved!!scheme is described. The circuit achieves a very low power operation with the large dynamic range required for audio applications. This modified two channel time- interleaved scheme improves the power efficiency thanks to halved operating frequency in the paths, and a reduced number of levels in ADC and DAC. This sigma-delta modulator fabricated in a 0.18!m CMOS process uses 1.8 V supply and ±0.5 V input range. Experimental results show that with a -35 dB FS input sine wave there are no tones above a -110 dB noise floor. I. INTRODUCTION The growing need of integrating audio systems in deep submicron technology is challenging for designing data converters as they need high resolution with low power consumption. Namely, the performance of audio ADCs becomes demanding for portable applications with MEMS silicon microphones. The trend is to convert the data immediately after the microphone and transmit on a single- wire bus the digital data. The solution is the optimum for reducing the noise interference provided that the power consumption is very low and the data transmission is in the ten kHz range (1), (2). The natural solution is using the sigma-delta (!!) technique as it can employ inaccurate analog elements that are available in sub-micron CMOS technologies. Nevertheless, since the sigma-delta modulator is not particularly power effective with audio bands it is necessary to identify the specific architecture that properly meets power and performances requests. This paper describes a sigma-delta modulator for audio band and medium sound quality as required by telephony applications. The key request is a dynamic range higher than 85 dB with a THD+N better than 40 dB at -40 dBv input. The specifications at higher input amplitude are less stringent because of the logarithmic hear response. The power consumption of!!modulators is mainly determined by the power of the amplifiers and the dissipation of the quantizer. Since the power of the amplifier increases as the square of the sampling frequency, reducing the sampling rate saves power. Moreover, the use of a quantizer with many levels leads to higher power in the quantizer but reduces the oversampling-rate saving power in the amplifiers. Therefore, the trade-off between quantizer levels and oversampling ratio is an important design issue. The design described below uses two time-interleaved (TI) paths for decreasing by two the sampling frequency of each path with unchanged overall clock speed and oversampling ratio (3). Moreover, reducing both the number of comparators used in the ADCs and the number of levels used in the DACs optimizes the use of power. The techniques that obtain the reduction, circuit schematic and the results of the experimental test are given in the next sections.
Year
DOI
Venue
2007
10.1109/ISCAS.2007.378598
New Orleans, LA
Keywords
Field
DocType
sampling frequency,dynamic range,power efficiency,high resolution,cmos technology,frequency,circuits,sampling methods,sigma delta modulator,data transmission,acoustic noise,delta sigma modulation
Electrical efficiency,Audio signal,Dynamic range,Noise floor,Computer science,Delta-sigma modulation,Electronic engineering,Modulation,CMOS,Electrical engineering,Sine wave
Conference
ISSN
ISBN
Citations 
0271-4302
1-4244-0921-7
1
PageRank 
References 
Authors
0.40
6
2
Name
Order
Citations
PageRank
Franco Maloberti1686144.70
Choi, Yonyoung210.40