Name
Title | ||
|---|---|---|
Design and Test of a CMOS MLP Analog Neural Network for Fast On-Board Signal Processing |
Abstract | ||
|---|---|---|
The feedforward multi-layer perceptron (MLP) type neural network (NN) presented in this paper has been developed for on-board applications of high-speed signal processing (240 MHz). It is fully analog in order to avoid analog-digital conversions and to limit chip size and power consumption. It is constituted by a single input, ten neurons in the hidden layer and a single output. The MLP-NN has been implemented in a 84 pins -0.6mum CMOS ASIC. The NN layout size is 1.8mmx0.7mm and the consumption is intended less than 600mW. This paper presents the design and simulations of each implemented cell and the first experimental tests achieved on the implemented ASIC. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ICECS.2006.379940 | ICECS |
Keywords | Field | DocType |
CMOS analogue integrated circuits,application specific integrated circuits,integrated circuit design,integrated circuit testing,multilayer perceptrons,signal processing,CMOS ASIC,CMOS MLP analog neural network,analog-digital conversions,chip size,fast on-board signal processing,feedforward multilayer perceptron type neural network,frequency 240 MHz,power consumption,size 0.6 mum,size 0.7 mm,size 1.8 mm | Signal processing,Computer science,Electronic engineering,Application-specific integrated circuit,CMOS,Integrated circuit design,Artificial neural network,Perceptron,Power consumption,Feed forward | Conference |
ISBN | Citations | PageRank |
1-4244-0395-2 | 3 | 0.52 |
References | Authors | |
1 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gatet, L. | 1 | 3 | 0.52 |
| Tap-Beteille, H. | 2 | 3 | 0.52 |
| M. Lescure | 3 | 5 | 1.64 |