Name
Abstract | ||
|---|---|---|
A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/JSSC.2007.900289 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
CMOS logic circuits,frequency dividers,oscillators,phase locked loops,LC-oscillator-based injection-locked frequency divider,charge pump PLL,frequency 50 GHz,logic CMOS process,phase-locked loop,self-oscillation frequency,size 0.13 mum,voltage-controlled oscillator,CMOS,injection-locked frequency divider (ILFD),millimeter-wave,phase-locked loop (PLL),push-push voltage-controlled oscillator (VCO) | Journal | 42 |
Issue | ISSN | Citations |
8 | 0018-9200 | 1 |
PageRank | References | Authors |
0.41 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Cao | 1 | 92 | 14.45 |
| Yanping Ding | 2 | 41 | 7.00 |
| Kenneth K. O | 3 | 249 | 42.87 |