Title | ||
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A 10-bit 205-MS/s 1.0- mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications |
Abstract | ||
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This paper describes a 10-bit 205-MS/s pipeline analog-to-digital converter (ADC) for flat panel display applications with the techniques to alleviate the design limitations in the deep-submicron CMOS process. The switched source follower combined with a resistor-switch ladder eliminates the sampling switches and achieves high linearity for a large single-ended input signal. Multistage amplifiers adopting the complementary common-source topology increase the output swing range with lower transconductance variation and reduce the power consumption. The supply voltage for the analog blocks is provided by the low drop-out regulator for a high power-supply rejection ratio (PSRR) under the noisy operation environment. The pipeline stages of the ADC are optimized in the aspect of power consumption through the iterated calculation of the sampling capacitance and transconductance. The ADC occupies an active area of 1.0 mm2 in a 90-nm CMOS process and achieves a 53-dB PSRR for a 100-MHz noise tone with the regulator and a 55.2-dB signal-to-noise-and-distortion ratio for a 30-MHz 1.0-VPP single-ended input at 205 MS/s. The ADC core dissipates 40 mW from a 1.0-V nonregulated supply voltage. |
Year | DOI | Venue |
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2007 | 10.1109/JSSC.2007.908760 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
cmos integrated circuits,amplifiers,analogue-digital conversion,capacitance,flat panel displays,ladder networks,cmos pipeline adc,analog blocks,analog-to-digital converter,deep-submicron cmos process,flat panel display,high power-supply rejection ratio,multistage amplifiers,resistor-switch ladder,signal-to-noise-and-distortion ratio,size 90 nm,switched source follower,transconductance,cmos analog integrated circuits,analog-to-digital converter (adc),buffer circuits,integrated circuit testing,low drop-out regulator,low power,low voltage,noise measurement,pipeline stage optimization,power-supply rejection ratio (psrr),sample-and-hold (s/h) circuits,switched-capacitor circuits,voltage regulators,amplifier,iterative method,integrated circuit,circuit switched,miniaturization,switching,sampling,optimization,power supply rejection ratio,switched capacitor circuits,resistor | Journal | 42 |
Issue | ISSN | Citations |
12 | 0018-9200 | 6 |
PageRank | References | Authors |
0.98 | 4 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
Seung-Chul Lee | 1 | 124 | 18.27 |
Young-Deuk Jeon | 2 | 98 | 13.50 |
Jong-Kee Kwon | 3 | 158 | 23.10 |
Kim, Jongdae | 4 | 6 | 0.98 |