Name
Abstract | ||
|---|---|---|
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software and hardware execution model. More recently, FPGAs, using new design tools, have also provided support for partial reconfiguration. The CSoC system designer is left with the task of interfacing IP Cores to the CPU and also for realizing partial reconfiguration across the cores. In this paper, we describe a software tool to automate the interface between the CPU and the reconfigurable fabric. Our tool generates hardware wrappers for the IP Cores that makes them look like a C function invocation in the source code. We also use our tool to support partial reconfiguration: the same wrapper is used for a multitude of IP Cores and the user selects the core to be invoked in the program. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ICCD.2006.4380805 | San Jose, CA |
Keywords | Field | DocType |
coprocessors,field programmable gate arrays,industrial property,logic CAD,program compilers,software libraries,system-on-chip,C function invocation,CPU,CSoC system design,FPGA,ROCCC compiler infrastructure,Xilinx Logicore IP Core library,configurable systems on a chip,dynamic co-processor architecture,partial reconfiguration,software acceleration,software tool | Computer science,Source code,Interfacing,Real-time computing,Software,Coprocessor,Multi-core processor,Control reconfiguration,Central processing unit,Computer architecture,System on a chip,Parallel computing,Embedded system | Conference |
ISSN | ISBN | Citations |
1063-6404 E-ISBN : 978-0-7803-9707-1 | 978-0-7803-9707-1 | 3 |
PageRank | References | Authors |
0.44 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abhishek Mitra | 1 | 142 | 10.24 |
| Zhi Guo | 2 | 191 | 15.14 |
| Anirban Banerjee | 3 | 3 | 0.78 |
| Najjar, Walid A. | 4 | 2011 | 183.19 |