Name
Title | ||
|---|---|---|
A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC |
Abstract | ||
|---|---|---|
This paper presents a reconfigurable, bit-sliced, scalable Montgomery multiplier architecture which can operate in both prime and binary fields, that is, GF(p) and GF(2n). It can be configured for any bit length thus making it applicable for emerging elliptic curve cryptography (ECC) as well as widely used RSA cryptosystems. Existing word-based, scalable multiplier architectures perform well for key sizes in RSA (but not ECC) as they result in higher computational time. Limited utility of word-based architectures for ECC precisions, which are in general not equal to an integer multiple of word-size, is discussed and a new bit-sliced architecture to improve the performance in terms of delay is proposed. The new bit-sliced, scalable architecture computes the Montgomery multiplication with fewer clock cycles compared to existing architectures by configuring them at bit-level rather than at word-level, without compromising on the performance. Synthesis results (Mentor Graphic’s Leonardo Spectrum) are compared with that of other scalable architectures and discussed. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VLSISOC.2007.4402507 | Atlanta, GA, USA |
Keywords | Field | DocType |
registers,montgomery multiplication,elliptic curve cryptography,very large scale integration,computer architecture,high performance computing,spectrum | Bit-length,Prime (order theory),Supercomputer,Computer science,Parallel computing,Multiplier (economics),Cryptosystem,Elliptic curve cryptography,Very-large-scale integration,Scalability | Conference |
ISBN | Citations | PageRank |
978-1-4244-1710-0 | 5 | 0.48 |
References | Authors | |
7 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sudhakar, M. | 1 | 5 | 0.48 |
| Ramachandruni Venkata Kamala | 2 | 5 | 0.48 |
| M. B. Srinivas | 3 | 96 | 15.09 |