Name
Abstract | ||
|---|---|---|
A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13 mum CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15 times 15 mum2 a wide range of operating frequency up to 900 MHz with an energy consumption of 41fJ/bit. In the asynchronous scheme we demonstrate with electrodes 8 times 8 mum2 a vertical propagation of clock at 1.7 GHz and a propagation delay of 420 ps for general purpose signal with energy consumption of 80 f J/bit. Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 1013 bits transmitted. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/CICC.2007.4405670 | San Jose, CA |
Keywords | Field | DocType |
CMOS integrated circuits,error statistics,integrated circuit interconnections,integrated circuit reliability,3D capacitive interconnections,AC interconnections reliability,BER measurements,CMOS process,asynchronous receiver circuits,asynchronous transmitter circuits,capacitive coupling,frequency 1.7 GHz,frequency 900 MHz,high speed chip-to-chip communication,high speed interchip communication,size 0.13 mum,synchronous receiver circuits,synchronous transmitter circuits,wafer-level assembly flows | Asynchronous communication,Transmitter,Propagation delay,Computer science,CMOS,Chip,Capacitive sensing,Electronic engineering,Electrical engineering,Energy consumption,Capacitive coupling | Conference |
ISBN | Citations | PageRank |
978-1-4244-1623-3 | 0 | 0.34 |
References | Authors | |
6 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. Canegallo | 1 | 4 | 2.14 |
| A. Fazzi | 2 | 94 | 8.38 |
| Ciccarelli, L. | 3 | 28 | 3.60 |
| Magagni, L. | 4 | 21 | 2.01 |