Name
Abstract | ||
|---|---|---|
A 60-GHz phase-locked loop (PLL) with inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80 x 40 mum2. The active area of the PLL is 0.6 x 0.6 mm2. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ESSCIRC.2007.4430344 | Munich |
Keywords | DocType | ISSN |
cmos integrated circuits,millimetre wave integrated circuits,phase locked loops,phase noise,prescalers,cmos process,frequency 60 ghz,frequency 61 ghz to 63 ghz,inductor-less prescaler,phase-locked loop,power 78 mw,size 90 nm,voltage 1.2 v,chip,phase lock loop | Conference | 1930-8833 |
ISBN | Citations | PageRank |
978-1-4244-1125-2 | 9 | 3.20 |
References | Authors | |
7 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroaki Hoshino | 1 | 45 | 11.54 |
| ryoichi tachibana | 2 | 9 | 3.20 |
| Toshiya Mitomo | 3 | 78 | 19.84 |
| naoko ono | 4 | 9 | 3.20 |
| Yoshiaki Yoshihara | 5 | 52 | 13.54 |
| Ryuichi Fujimoto | 6 | 24 | 14.44 |