Name
Abstract | ||
|---|---|---|
A multistandard WLAN fractional-N frequency synthesizer is implemented in 0.13-mum CMOS. The PLL is able to generate carrier frequency for 802.11a/b/g and Hiper- LAN2 standards. Given the wide tuning range required, the VCO adopts a switched tuning LC tank together with an Adaptive Frequency Calibration (AFC) technique. Measured integral phase noise is less than 3deg rms and the 40-MHz reference spurs are below -40 dBc. Lock time is less than 200 musec. The power consumption is about 50 mW from a 1.2- V supply. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ESSCIRC.2007.4430346 | Munich |
Keywords | DocType | ISSN |
cmos integrated circuits,ieee standards,frequency synthesizers,phase locked loops,voltage-controlled oscillators,wireless lan,802.11abg wlan,cmos,adaptive frequency calibration,delta-sigma fractional-n frequency synthesizer,multistandard wlan fractional-n frequency synthesizer,phase locked loop,power 50 mw,size 0.13 micron,voltage 1.2 v,voltage-controlled oscillator,frequency synthesizer,phase noise | Conference | 1930-8833 |
ISBN | Citations | PageRank |
978-1-4244-1125-2 | 0 | 0.34 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andrea Bonfanti | 1 | 4 | 1.56 |
| Samori, C. | 2 | 12 | 1.24 |
| Lacaita, A.L. | 3 | 0 | 0.34 |