Name
Abstract | ||
|---|---|---|
With the growing security needs of applications such as homeland security or banking, the frequent updates in cryptographic standards and the high ASIC costs, the ciphering algorithms on an asynchronous embedded FPGA co-processor are becoming a viable alternative. Within the SAFE project, a novel architecture of asynchronous e-FPGA has been proposed. This architecture is natively robust against side channel attacks such as simple and differential power analysis or clock based fault attacks. Simulation-based security proofs are also presented. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/FPT.2007.4439288 | Kitakyushu |
Keywords | Field | DocType |
asynchronous circuits,cryptography,field programmable gate arrays,ASIC costs,asynchronous E FPGA architecture,ciphering algorithms,cryptographic standards,security applications,simulation based security proofs | Homeland security,Asynchronous communication,Power analysis,Architecture,Computer science,Cryptography,Field-programmable gate array,Application-specific integrated circuit,Side channel attack,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4244-1472-7 | 4 | 0.40 |
References | Authors | |
5 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Beyrouthy, T. | 1 | 4 | 0.40 |
| Razafindraibe, A. | 2 | 4 | 0.40 |
| laurent fesquet | 3 | 28 | 2.42 |
| Marc Renaudin | 4 | 498 | 49.15 |