Title
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
Abstract
As microprocessors enter the highly multi-core/multi-threaded era, higher density, lower latency embedded memory will be required to meet cache design needs. This paper describes a 500 MHz random cycle silicon on insulator (SOI) embedded DRAM macro which features a three-transistor micro sense amplifier, realizing significant performance gains over traditional array design methods. To address the realities of process integration, we describe the features and issues associated with integrating this DRAM into SOI technology, including deep trench processing and floating body effects. After a brief description of the macro architecture, details are provided on the three-transistor micro sense amplifier scheme, which is key to achieving a high transfer ratio with minimal area overhead. The paper concludes with hardware results and a summary.
Year
DOI
Venue
2008
10.1109/JSSC.2007.908006
Solid-State Circuits, IEEE Journal of
Keywords
Field
DocType
dram chips,uhf amplifiers,uhf integrated circuits,microprocessor chips,silicon-on-insulator,soi embedded dram macro,dynamic random-access memory,frequency 500 mhz,macro architecture,microprocessor,random cycle silicon on insulator,three-transistor microsense amplifier,time 1.5 ns,fet amplifiers,silicon on insulator,memory architecture,integrated circuit,thread,sense amplifier,gain,cache memory,field effect transistor,dynamic random access memory,embedded systems
Dynamic random-access memory,Sense amplifier,Dram,Cache,CPU cache,Computer science,Electronic engineering,Macro,Electrical engineering,Integrated circuit,Memory architecture
Journal
Volume
Issue
ISSN
43
1
0018-9200
Citations 
PageRank 
References 
30
6.45
5
Authors
17