Paper Info
Title
Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems
Abstract
This paper proposes Virtual Exclusion, an architectural technique to reduce leakage energy in the L2 caches for cache-coherent multiprocessor systems. This technique leverages two previously proposed circuits techniques — gated Vdd and drowsy cache, and proposes a low cost, easily implementable scheme for cache-coherent multiprocessor systems. The Virtual Exclusion scheme saves leakage energy by keeping the data portion of repetitive cache lines off in the large higher level caches while still manages to maintain Multi-Level Inclusion, an essential property for an efficient implementation of conventional cache coherence protocols. By exploiting the existing state information in the snoop-based cache coherence protocol, there is almost no extra hardware overhead associated with our scheme. In our experiments, the SPLASH-2 multiprocessor benchmark suite was correctly executed under the new Virtual Exclusion policy and showed an up to 72% savings of leakage energy (46% for SMP and 35% for multicore in L2 on average) over a baseline drowsy L2 cache.
Year
DOI
Venue
2007
10.1109/ICPADS.2007.4447739
Parallel and Distributed Systems, 2007 International Conference
Keywords
Field
DocType
cache storage,multiprocessing systems,power aware computing,protocols,L2 cache,leakage energy reduction,multiprocessor systems,snoop-based cache coherence protocol,virtual exclusion
CPU cache,Cache,Computer science,MESI protocol,Parallel computing,Real-time computing,Cache algorithms,Bus sniffing,Multi-core processor,Energy consumption,Cache coherence,Embedded system
Conference
Volume
ISSN
ISBN
2
1521-9097 E-ISBN : 978-1-4244-1890-9
978-1-4244-1890-9
Citations 
PageRank 
References 
7
0.46
12
Authors
2
Name
Order
Citations
PageRank
Mrinmoy Ghosh136722.39
Lee, H.-H.S.2816.84