Title | ||
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Hardware implementation of hierarchical volume subdivision-based elastic registration. |
Abstract | ||
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Real-time, elastic and fully automated 3D image registration is critical to the efficiency and effectiveness of many image-guided diagnostic and treatment procedures relying on multimodality image fusion or serial image comparison. True, real-time performance will make many 3D image registration-based techniques clinically viable. Hierarchical volume subdivision-based image registration techniques are inherently faster than most elastic registration techniques, e.g. free-form deformation (FFD)-based techniques, and are more amenable for achieving real-time performance through hardware acceleration. Our group has previously reported an FPGA-based architecture for accelerating FFD-based image registration. In this article we show how our existing architecture can be adapted to support hierarchical volume subdivision-based image registration. A proof-of-concept implementation of the architecture achieved speedups of 100 for elastic registration against an optimized software implementation on a 3.2 GHz Pentium III Xeon workstation. Due to inherent parallel nature of the hierarchical volume subdivision-based image registration techniques further speedup can be achieved by using several computing modules in parallel. |
Year | DOI | Venue |
---|---|---|
2006 | 10.1109/IEMBS.2006.259498 | Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference |
Keywords | DocType | Volume |
hardware acceleration,multimodality image fusion,software implementation,pentium iii xeon workstation,image-guided diagnostic procedure,hardware implementation,image-guided treatment procedure,hierarchical volume subdivision,elastic registration,image registration,field programmable gate arrays,fpga-based architecture,free-form deformation based technique,medical image processing,3d imaging,image fusion,proof of concept,hardware accelerator,real time | Conference | 1 |
ISSN | ISBN | Citations |
1557-170X | 1-4244-003303 | 4 |
PageRank | References | Authors |
0.44 | 4 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Dandekar, O. | 1 | 23 | 1.85 |
Vivek Walimbe | 2 | 4 | 0.44 |
Raj Shekhar | 3 | 24 | 3.15 |