Name
Abstract | ||
|---|---|---|
We present a ROM based logic design technique using reduced ROM size by eliminating identical rows and columns along with fast and low power single transistor cells. It substantially reduces the critical path length and thereby, improves the performance yet achieves low-power dissipation due to reduced number of switching. We present the ROM based design of a carry select adder (CSA) and two parallel prefix adders, which achieve more than 30% (in 32 bit adder) delay reduction over their conventional designs at 90 nm technology with as low as 9% (CSA) active power increase. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISCAS.2008.4541538 | Seattle, WA |
Keywords | Field | DocType |
adders,network synthesis,power transistors,read-only storage,switching circuits,ROM based logic design technique,carry select adder,high performance adders,low power adders,low power dissipation,low power single transistor cells,parallel prefix adders,read only memory,size 90 nm | Logic synthesis,Read-only memory,Adder,Power semiconductor device,Computer science,Carry-select adder,Electronic engineering,Carry-save adder,Critical path method,Transistor,Computer hardware | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4244-1684-4 | 1 |
PageRank | References | Authors |
0.45 | 2 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bipul Chandra Paul | 1 | 1 | 0.45 |
| Fujita, Shinobu | 2 | 46 | 2.35 |
| Masaki Okajima | 3 | 18 | 3.94 |