Name
Abstract | ||
|---|---|---|
A new architecture of a sampling rate converter for high oversampling delta-sigma analog-to-digital converters is presented. The proposed system using a negative feedback technique can greatly reduce the hardware, achieving the rate conversion of the large decimation ratio and the sufficient aliasing suppression with linear phase shift characteristic. A design example is given to demonstrate that the sine function. Compared with a conventional cascaded integrator-comb decimation Alter, a 67% area saving is achieved by the proposed converter. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISCAS.2008.4541819 | Seattle, WA |
Keywords | Field | DocType |
delta-sigma modulation,feedback,area-efficient sampling rate converter,decimation ratio,delta-sigma analog-to-digital converters,linear phase shift characteristics,negative feedback technique,sufficient aliasing suppression | Linear phase,Decimation,Oversampling,Computer science,Control theory,Sampling (signal processing),Negative feedback,Delta-sigma modulation,Electronic engineering,Aliasing,Quantization (signal processing) | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4244-1684-4 | 0 |
PageRank | References | Authors |
0.34 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masanori Furuta | 1 | 22 | 3.56 |
| Takafumi Yamaji | 2 | 0 | 0.34 |
| Takeshi Ueno | 3 | 1 | 0.96 |
| Tetsuro Itakura | 4 | 187 | 33.44 |