Name
Abstract | ||
|---|---|---|
We propose a macromodel for delay estimation at the RTL level. The macromodel is useful for approximating the delay through the critical path of an RTL block as a function of Vdd and Vt. It is specifically designed for delay estimation at the early phase of the design flow and based on detailed HSPICE analysis of NAND chains to extract the parameter values. This macromodel has two fitting parameters which make the macromodel simple but accurate. The steps needed to extract the two parameters are described. The validation of the model is demonstrated by comparison with HSPICE. According to our experiments, this macromodel is able to predict the delay variation due to Vdd and Vt with accuracy of plusmn3% at the logic level and plusmn5% for RTL blocks. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISCAS.2008.4541946 | Seattle, WA |
Keywords | Field | DocType |
NAND circuits,SPICE,VLSI,delay estimation,HSPICE analysis,NAND chains,delay estimation,delay macromodeling | Delay calculation,Computer science,Spice,NAND gate,Electronic engineering,Design flow,Logic level,Critical path method,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4244-1684-4 | 4 |
PageRank | References | Authors |
0.38 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tatsuya Koyagi | 1 | 4 | 0.38 |
| Masahiro Fukui | 2 | 42 | 14.57 |
| R. Saleh | 3 | 13 | 1.39 |