Name
Abstract | ||
|---|---|---|
With reducing feature sizes, SRAM stability has become a major concern for future technologies. This critical issue can be solved by using highly stable separate bit-line read SRAM cell, but access time improvement becomes critical, since differential sense amplifier cannot be used for single bit-line read operation. In this paper, a novel pseudo differential single ended current mode sense amplifier is proposed. We demonstrate that this design can deliver a performance similar to that of conventional current mode differential amplifier without using dual bit-line for read operation. The overall read operation delay of the proposed single-ended design is almost 60% less than conventional single-ended design in 90 nm CMOS technology. The proposed design consumes 51.6% less energy than conventional design counterpart. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISCAS.2008.4542171 | Seattle, WA |
Keywords | Field | DocType |
CMOS integrated circuits,SRAM chips,differential amplifiers,CMOS technology,SRAM cell,current sense amplifier,high speed amplifier,single-ended pseudo differential amplifier | Current-feedback operational amplifier,Sense amplifier,Fully differential amplifier,Computer science,Direct-coupled amplifier,Operational transconductance amplifier,Electronic engineering,Linear amplifier,Current sense amplifier,Electrical engineering,Operational amplifier | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4244-1684-4 | 2 |
PageRank | References | Authors |
0.46 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abhijit Sil | 1 | 2 | 0.46 |
| Eswar Prasad Kolli | 2 | 2 | 0.46 |
| Soumik Ghosh | 3 | 63 | 5.17 |
| Magdy A. Bayoumi | 4 | 803 | 122.04 |