Name
Abstract | ||
|---|---|---|
A zero-overhead dynamic optically reconfigurable gate array (ZO-DORGA), based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory, has been proposed to realize both a high gate-count and zero-overhead rapid reconfiguration. This paper presents the world’s largest 11,424 gate-count zero-overhead VLSI chip fabricated on a 96.04 mm2 chip using 0.35 μm-3 metal CMOS process technology. The optical reconfiguration circuit, the gate array structure, the CAD layout, and the performance of ZO-DORGA-VLSI are described, with reference to experimental results related to the reconfiguration period and retention time. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/SOCC.2007.4545430 | Hsin Chu, Taiwan |
Keywords | Field | DocType |
field programmable gate arrays,capacitance,holography,circuits,photodiodes,very large scale integration | Gate count,Capacitance,Computer science,Field-programmable gate array,Chip,Electronic engineering,Diffusion capacitance,Gate array,Electrical engineering,Very-large-scale integration,Control reconfiguration | Conference |
ISSN | ISBN | Citations |
2164-1676 | 978-1-4244-1593-9 | 1 |
PageRank | References | Authors |
0.41 | 2 | 1 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Minoru Watanabe | 1 | 1 | 0.41 |