Name
Abstract | ||
|---|---|---|
Data prefetching is a well known approach to compen- sating for poor memory performance, and has been em- ployed in commercial processor chips. Although a num- ber of prefetching techniques have so far been proposed, in many cases, they have assumed single-core architec- tures. In Chip MultiProcessor (or CMP) chips, there are some shared resources such as L2 caches, buses, and so on. Therefore, the effect of prefetching on CMP should be dif- ferent from traditional single-core processors. In this paper, we analyze the effect of prefetching on CMP performance. This paper first classifies the impact of prefetches issued during program execution. Then, we discuss quantitatively the effect of prefetching to memory performance. The experimental results show that the nega- tive effect of invalidation of prefetched cache blocks is very small. In addition, it is observed that the current prefetch algorithms do not exploit effectively the feature of CMPs, i.e. cache-to-cache on-chip data transfer. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/APCSAC.2008.4625454 | Hsinchu |
Keywords | Field | DocType |
cache storage,microprocessor chips,L2 caches,cache-to-cache on-chip data transfer,chip multiprocessors,commercial processor chips,data prefetching,memory performance,program execution,single-core processors | System on a chip,Data transmission,Computer science,Cache,Parallel computing,Chip,Multiprocessing,Exploit,Instruction prefetch,Benchmark (computing) | Conference |
ISBN | Citations | PageRank |
978-1-4244-2683-6 | 0 | 0.34 |
References | Authors | |
5 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Naoto Fukumoto | 1 | 0 | 0.68 |
| Tomonobu Mihara | 2 | 0 | 0.34 |
| Koji Inoue | 3 | 370 | 42.28 |
| Kazuaki Murakami | 4 | 394 | 51.44 |