Name
Abstract | ||
|---|---|---|
This paper describes the architecture and design flow of a self-reconfigurable embedded system, mapped on a Spartan-3 low-cost FPGA, where a fixed area is reserved to accommodate a reconfigurable coprocessor. Spartan-3 low-cost family lacks of the ICAP (Internal Configuration Access Port) and design tools for self-reconfiguration. The paper also deals with other issues, such as OPB isolation, bit-stream retrieve from external SRAM, bit-stream processing, and clock routing. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/FPL.2008.4630011 | Heidelberg |
Keywords | Field | DocType |
coprocessors,embedded systems,field programmable gate arrays,network routing,reconfigurable architectures,SRAM external memory controller,Spartan-3,bit-stream processing,clock routing,field programmable gate arrays,internal configuration access port,reconfigurable coprocessor,self-recofigurable embedded systems | Architecture,Spartan,Computer science,Network routing,Parallel computing,Field-programmable gate array,Static random-access memory,Real-time computing,Design flow,Coprocessor,Clock routing,Embedded system | Conference |
ISSN | ISBN | Citations |
1946-1488 | 978-1-4244-1961-6 | 0 |
PageRank | References | Authors |
0.34 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Enrique Cantó | 1 | 0 | 0.34 |
| Francesc Fons | 2 | 0 | 0.34 |
| Mariano López | 3 | 0 | 0.34 |